The present invention relates to the structure of a thin film transistor used as, e.g., the switching element of a liquid crystal display, and a manufacturing process therefor, and relates to a thin film transistor array using a thin film transistor with the above structure, and the structure of an active matrix liquid crystal display.
An active matrix liquid crystal display using a twisted nematic (TN) liquid crystal has excellent characteristics such as a large capacity and a high density, and is widely used for a television image display, a graphic display, and the like.
To provide a high-contrast display free from any crosstalk, such an active matrix liquid crystal display employs a scheme of driving and controlling each pixel by using a semiconductor switching element. The semiconductor switching element for this application is often a thin film transistor (TFT) in which a semiconductor active layer (channel, source, and drain regions) is formed of amorphous silicon (a-Si) on a glass substrate because it is capable of transmission type display and its area can be relatively easily increased.
Generally known structures of such amorphous silicon TFTs are an inverted staggered TFT in which the gate electrode is arranged below the amorphous silicon layer serving as an active layer, a staggered TFT in which the gate electrode is arranged above the amorphous silicon layer.
Of these structures, the inverted staggered TFT has good transistor characteristics. However, since the gate electrode is arranged underneath the amorphous silicon layer, the resistance of the gate electrode wiring line (scanning line) is difficult to decrease. When a TFT is applied to an active matrix liquid crystal display, of the constituent elements of the TFT, the gate electrode wiring line needs to have low resistance. This problem becomes more serious when the LCD is large in size. As for the productivity, 6 or more photomasks are normally required for the inverted staggered structure, so a cost reduction is difficult to attain.
In the staggered TFT, the gate electrode is arranged above the amorphous silicon layer (top gate type), and the source and drain electrodes are arranged below the amorphous silicon layer. The staggered TFT is advantageous in terms of the productivity and the manufacturing cost because the number of photomasks can be minimized to 2. In addition, since the staggered TFT is of the top gate type, Al can be used as the material of the gate electrode wiring line and it is easy to form a thick film.
However, this conventional staggered structure also has the following problems. First, it is difficult to obtain an ohmic contact between n+ a-Si formed on the source and drain electrodes and a-Si of the active layer, therefore a sufficient ON current cannot be ensured for the TFT. Although it has been proposed to use ITO (Indium Tin Oxide) for the source and drain electrodes and to process the ITO surface with a PH3 plasma before formation of a-Si, the a-Si layer formed subsequently is adversely affected due to contamination with P. In addition, since the source and drain electrodes overlap the gate electrode, the parasitic capacitances between the gate and source and between the gate and drain increase.
U.S. Pat. No. 4,727,044 discloses the following process for manufacturing a top gate TFT. That is, an amorphous silicon layer is formed on a glass substrate, and a gate electrode is formed on this amorphous silicon layer via a gate dielectric layer. Using this gate electrode as a mask, ion doping and laser irradiation are performed for the amorphous silicon layer at portions corresponding to source and drain regions to crystallize the amorphous silicon layer in the regions. The amorphous silicon layer at a portion masked by the gate electrode constitutes a channel. When this process is used to manufacture a coplanar type TFT which is one of top gate TFTs and employed in a monocrystalline silicon LSI, the following process is further performed. The gate electrode and the source and drain regions are covered with an insulating protective layer, a contact hole is formed in this insulating protective layer, and source and drain electrodes are formed.
However, the above TFT structure disclosed in U.S. Pat. No. 4,727,044 has the following problems.
In an application to a liquid crystal display, the amorphous silicon layer must be processed into an island shape, and the semiconductor layer must be isolated between adjacent TFTs. In this case, the amorphous silicon layer is processed into an island shape before formation of a gate dielectric layer. However, a clean interface (channel interface) between the amorphous silicon layer and the gate dielectric layer is difficult to provide, so a TFT having high mobility and high reliability cannot be obtained.
In doping ions into the amorphous silicon layer corresponding to the source and drain regions, a very large acceleration voltage is required because the ions are doped through the gate dielectric layer into the underlying amorphous silicon layer. In the process for manufacturing a monocrystalline silicon LSI, ions are normally doped through a gate dielectric layer. Ion doping through the gate dielectric layer is possible because the thickness of the gate dielectric layer is as thin as 50 nm or less. To the contrary, in a TFT used for a liquid crystal display, a gate dielectric layer generally also serves as an interlevel insulating layer between scanning and signal lines in order to decrease the number of steps. To ensure the insulation properties, or to reduce the capacitance at the cross portion between the scanning and signal lines, the thickness of the gate dielectric layer is set to about 200 to 500 nm. With such a thickness, ions cannot reach the amorphous silicon layer even at an ion doping acceleration voltage of 100 kV; in practice, ion doping through the gate dielectric layer is impossible.
In crystallizing the amorphous silicon layer by laser irradiation, if the laser is irradiated through the gate dielectric layer, ablation easily occurs to scatter amorphous silicon along with discharge of a gas, such as hydrogen gas, from the amorphous silicon layer. In addition to ablation, since interference of the laser beam is caused by the dielectric layer on the amorphous silicon layer, the intensity of the laser beam incident on the amorphous silicon layer undesirably changes in correspondence with variations in thickness of the dielectric layer.
As described above, the amorphous silicon layer cannot be stably crystallized by irradiating the laser through the gate dielectric layer.
The present invention has been made in consideration of the above situation, and has as its object to provide a manufacturing process and structure of a thin film transistor having high productivity in which a clean interface can be formed between a channel and a gate dielectric layer, and the resistance of a gate electrode wiring line (scanning line) is easily decreased, a semiconductor active layer and source and drain electrodes reliably form an ohmic contact, and the number of masks required in the manufacturing process can be decreased.
According to the present invention, there is provided a process for manufacturing a thin film transistor, which comprises the steps of:
depositing an amorphous silicon layer on an insulating substrate;
depositing a 1-st gate dielectric layer consecutively to the step of depositing the amorphous silicon layer;
patterning the amorphous silicon layer together with the 1-st gate dielectric layer into an island shape;
depositing a 2-nd gate dielectric layer to cover the 1-st gate dielectric layer patterned into the island shape;
depositing a conductive layer on the 2-nd gate dielectric layer;
patterning the conductive layer to form a gate electrode; and
doping an impurity ion into the amorphous silicon layer by using the gate electrode as a mask.
According to the thin film transistor manufacturing process of the present invention, the gate dielectric layer is constituted by the 1-st and 2-nd two gate dielectric layers. After the amorphous silicon layer serving as a semiconductor layer is processed together with the 1-st gate dielectric layer into an island shape, they are covered with the 2-nd gate dielectric layer. By employing this step, no patterning step is interposed between deposition of the amorphous silicon layer and deposition of the 1-st gate dielectric layer. The amorphous silicon layer and the 1-st gate dielectric layer can be consecutively deposited by plasma CVD in the same reactive chamber, while maintaining the vacuum state. As a result, a clean interface (channel interface) can be easily obtained between the amorphous silicon layer and the gate dielectric layer. A TFT excellent in characteristics such as high mobility and high reliability can be manufactured.
Since the amorphous silicon layer is processed into an island shape before formation of the gate electrode, semiconductor layers of adjacent TFTs are completely isolated from each other in constituting a TFT array, and no field TFT is formed.
Since the doping element is sufficiently activated due to poly-crystallization by laser irradiation in the source and drain regions formed in self-alignment using the gate electrode as a mask, the resistance of these regions is lower than that of n+ a-Si (n-type amorphous silicon) formed by conventional CVD. For this reason, satisfactory ohmic contact can be ensured between the source region and the source electrode and between the drain region and the drain electrode. As a result, an improvement in TFT characteristics and a reduction in parasitic capacitance, which have been subjects in a TFT with a top gate structure using amorphous silicon for an active layer, can be simultaneously attained.
At least the 2-nd gate dielectric layer is removed by etching using the gate electrode as a mask before the step of doping an impurity ion. With this step, ions can be doped in the amorphous silicon even at a low acceleration voltage.
The 2-nd and 1-st gate dielectric layers are preferably removed by etching using the gate electrode as a mask to expose the surface of the amorphous silicon layer before the step of doping an impurity ion. If a dielectric layer exists on the amorphous silicon layer, the amorphous silicon layer readily causes ablation upon laser irradiation. From this viewpoint, the surface of the amorphous silicon layer is preferably exposed before ion doping.
When silicon nitride is used for the gate dielectric layer, it is etched using the same resist pattern as that used for etching of the gate electrode. At this time, if the gate electrode is side-etched, the gate electrode and the source/drain region are apt to form a short-circuit, or the gate electrode overhanging like a peak may form a shadow in ion doping and laser irradiation to degrade the TFT characteristics. Therefore, side etching must be prevented. Further, etching having a high selectivity must be employed to leave the lower amorphous silicon layer. An effective method which satisfies both the conditions is reactive ion etching using a gas mixture of at least C, H, and F, such as a gas mixture of CHF3 and O2 or a gas mixture of CF4 and H2.
In the thin film transistor manufacturing process of the present invention, the source and drain electrodes can be respectively arranged either below or above the source and drain regions.
In the former case, i.e., when the source electrode is arranged between the source region and the insulating substrate, and the drain electrode is arranged between the drain region and the insulating substrate, the thin film transistor is manufactured by the following process. Prior to deposition of the amorphous silicon layer, the source and drain electrodes are formed to have a larger interval therebetween than the width of the gate electrode to be formed in a subsequent step. After the amorphous silicon layer is deposited, it is poly-crystallized by ion doping and laser irradiation using the gate electrode as a mask. With this process, the channel length is determined in self-alignment with the gate electrode. At this same time, the source and drain electrodes are respectively connected to the low-resistance source and drain regions.
In this case, it is important that the gate dielectric layer and the gate electrode be etched using the same pattern to expose the surface of the amorphous silicon layer before ion doping. This is because an impurity must be deeply doped in the amorphous silicon layer in order to connect the source and drain electrodes to the lower surface of the low-resistance polycrystalline silicon layer.
The material for the source and drain electrodes must be a low-resistance, refractory material so as to resist the high temperature during laser irradiation. From this viewpoint, an MoW alloy and an MoTa alloy are desirable materials which satisfy both the requirements. Particularly, the MoW alloy is more preferable than the MoTa alloy because its resistance is lower.
In the latter case, i.e., when the source and drain electrodes are respectively arranged above the drain and source regions, the thin film transistor is manufactured by the following process. After the gate electrode and 2-nd and 1-st gate dielectric layers are patterned, similar to the former case, impurity ions are doped in the amorphous silicon layer at portions corresponding to the source and drain regions by using the gate electrode as a mask. After metal thin films are deposited in the regions, the amorphous silicon layer is heat-treated and the metal thin films are removed by etching. With this process, the surface of the amorphous silicon surface is changed into a metal silicide to form the source/drain region.
In this manufacturing process, a metal silicide is formed on the surface, of the amorphous silicon layer, in the region doped with the impurity ions, thereby decreasing the resistance of this region. Also in this case, a self-aligned TFT can be formed without impairing the current driving ability of the TFT. Further, satisfactory ohmic contact can be formed between the source region and the source electrode, and between the drain region and the drain electrode. Therefore, an improvement in TFT characteristics and a reduction in parasitic capacitance, which have been subjects in a TFT with a top gate structure using amorphous silicon as an active layer, can be simultaneously attained. Note that a suitable metal for silicidation is Mo, Ti or W.
In the above thin film transistor, a light shield layer consisting of an amorphous silicon carbide layer is preferably arranged below the thin film transistor. In this case, an insulating layer is further arranged between the insulating substrate and the amorphous silicon layer, and the light shield layer is arranged between the insulating substrate and this insulating layer. Alternatively, the light shield layer can be directly arranged between the insulating substrate and the amorphous silicon layer.
It has conventionally been known to use an amorphous silicon layer as a light shield layer. However, since the amorphous silicon layer has a low resistance, and becomes conductive upon light irradiation, the TFT characteristics are influenced; the threshold voltage shifts due to the back gate effect arising from electric charges in the light shield layer. In the present invention, since a silicon carbide film (SiCx) is used as the light shield layer, a high-resistance light shield layer having a photoconductivity two orders of magnitudes or more lower than that of the amorphous silicon layer can be obtained. Although the silicon carbide layer is slightly lower in light shield ability than the amorphous silicon layer because its band gap is wider, a proper layer can be attained by adjusting the content of C.
It is preferable that a semiconductor film forming an active layer be constituted by two layers, amorphous silicon and SiCx be respectively used for its upper and lower layer portions, and the lower SiCx layer be used as a light shield layer. If the light shield layer is formed in this manner, even when light is irradiated on the light shield layer, the leakage current from the TFT can be suppressed to a negligible level because of a short lifetime of emission carriers. Therefore, a TFT having high light resistance can be obtained.
According to the present invention, there is provided an array substrate using thin film transistors as switching elements, comprising:
an insulating substrate;
amorphous silicon layers formed into an island shape and two-dimensionally arrayed on the insulating substrate, each amorphous silicon layer having a channel region, and source and drain regions formed on two sides of the channel region;
1-st gate dielectric layers formed on the amorphous silicon layers so as to cover the channel regions;
2-nd gate dielectric layers formed on the 1-st gate dielectric layers;
gate electrodes formed on the 2-nd gate dielectric layers;
source electrodes connected to the source regions;
drain electrodes connected to the drain regions;
pixel electrodes two-dimensionally arrayed on the insulating substrate, each pixel electrode being electrically connected to each source electrode;
signal lines formed integrally with the drain electrodes, the signal lines being arrayed between adjacent pixel electrodes; and
scanning lines formed integrally with the gate electrodes, the scanning lines crossing the signal lines, and being arranged above the signal lines via the 2-nd gate dielectric layers.
In the above thin film transistor array substrate, the source and drain electrodes can be arranged either below or above the source and drain regions respectively. The pixel electrode can be arranged either above or below the source and drain electrodes.
When the pixel electrodes are arranged above the source and drain electrodes, an insulating protective layer is deposited to cover the signal lines and the scanning lines, and the pixel electrodes are arranged above this insulating protective layer. The pixel electrodes are electrically connected to the source electrodes through 1-st contact holes formed in the insulating protective layer.
The thin film transistor array having the above structure is manufactured by, e.g., the following process.
Signal lines are arrayed on an insulating substrate. Drain electrodes are formed on the insulating substrate integrally with the signal lines in the same step as that for the signal lines. At the same time, source electrodes are formed on the insulating substrate. Thin film transistors each having the above structure are formed on the drain and source electrodes formed in this manner. Scanning lines are formed integrally with gate electrodes in the same step as that for the gate electrodes. The 2-nd gate dielectric layers are also used as interlevel insulating layers between the scanning and signal lines. An insulating protective layer is deposited to cover the upper surfaces of the insulating substrate, the thin film transistors, and the signal and scanning lines. 1-st contact holes are formed in the insulating protective layer to partially expose the source electrodes. Pixel electrodes are formed in those regions, of the upper surface of the insulating protective layer, that are above the respective regions defined by the signal and scanning lines. The pixel electrodes are connected to the source electrodes through the 1-st contact holes.
In the thin film transistor array having the structure in which the pixel electrodes are arranged above the thin film transistors, the opening ratio of the LCD can be increased.
When the pixel electrodes are arranged above the source and drain electrodes, the thin film transistor array is preferably constituted as follows. That is, lower capacitor electrodes are formed on the insulating substrate in the same step as that for the signal lines. The pixel electrodes are connected to the lower capacitor electrodes through 2-nd contact holes formed in the insulating protective layer to constitute auxiliary capacitors between the lower capacitor electrodes and the scanning lines. In the above structure, each lower capacitor electrode is connected to the source electrode through the pixel electrode. In this manner, since the two electrodes are connected through the pixel electrode consisting of the transparent conductive thin film, the opening ratio of the LCD can be increased.
When the pixel electrodes are arranged above the source and drain electrodes, the thin film transistor array is preferably constituted as follows. That is, the signal lines are formed such that the edge portions of the pixel electrodes overlap the signal lines via the insulating protective layer to make the signal lines function as black matrixes. With this structure, the opening ratio of the LCD can be further increased because no margin for the mask alignment precision is required, compared to a conventional case in which black matrixes are formed independently.
When, however, this structure is simply employed, the coupling capacitance between the pixel electrode and the signal line may increase due to overlapping therebetween. This coupling capacitance may pose a problem such as crosstalk generated on the display of the LCD. To solve this problem, the thin film transistor array is constituted as follows. That is, shield electrodes are arranged above the signal lines through the 2-nd gate dielectric layers. The shield electrodes can be formed integrally with the scanning lines in the same step as that for the scanning lines. The pixel electrodes are formed such that their edge portions overlap the shield electrodes via the insulating protective layer. With this arrangement, the shield electrodes are made to function as black matrixes. At the same time, auxiliary capacitors are constituted between the shield electrodes and the pixel electrodes.
Since the shield electrodes are interposed between the pixel electrodes and the signal lines, the electric field is sealed to prevent variations in potentials of the signal lines from influencing the pixel potentials. In the thin film transistor having the above structure, the shield electrode can be realized by the auxiliary capacitor line formed in the same step as that for the scanning line (i.e., gate electrode), or the scanning line itself of an adjacent pixel. The shield structure can be fabricated without adding a special step. The black matrix structure is desirably formed by making the edge portions of the pixel electrodes overlap the shield electrodes. In this case, it is preferable in terms of the yield that the edge portions of the pixel electrodes be not made to overlap the signal lines.
When the pixel electrodes consist of ITO (Indium Tin Oxide), the insulating protective layer is preferably made of silicon oxide or silicon oxynitride.
Particularly when the edge portions of the pixel electrodes consisting of ITO overlap the signal lines, or when the edge portions of the pixel electrodes consisting of ITO overlap the shield electrodes, dry etching is desirably employed because etching of ITO requires a high processing precision. Known dry etching for ITO is reactive ion etching using hydrogen iodide (HI) gas, hydrogen bromide (HBr) gas, or hydrogen chloride (HCl) gas. If silicon nitride is used for an underlayer, the etching selectivity is only about 3 even with HI gas having the highest selectivity, decreasing the thickness of silicon nitride. However, if silicon oxide or silicon oxynitride is used for the underlayer, and HI is used for the etching gas, a selectivity of about 10 can be obtained. ITO can be dry-etched while suppressing a decrease in thickness of the protective layer to a negligible level.
A thin film transistor array in which the pixel electrodes are arranged above the source and drain electrodes is manufactured by, e.g., the following process.
A transparent conductive thin film (e.g., ITO) is first deposited on an insulating substrate, and a metal thin film is deposited thereon. The metal thin film and the transparent conductive thin film are simultaneously patterned to simultaneously form signal lines stacked on the transparent conductive thin film, drain electrodes integral with the signal lines, and pixel electrodes covered with the metal thin film. Thin film transistors each having the above structure, and scanning lines are formed on the obtained structure. After an insulating protective layer is deposited on the resultant structure, the insulating protective layer in pixel electrode regions is removed by etching. Further, the metal thin film in the regions is removed by etching to form source electrodes. According to the above process, the number of patterning steps required to form a thin film transistor array can be decreased by one.
It is theoretically possible to perform simultaneous processing of the pixel electrode and the signal line in an inverted staggered TFT with a bottom gate structure and a conventional staggered TFT. However, in the inverted staggered TFT, the contact portion between the source and drain regions has a structure in which ITO is connected to an n+ a-Si layer. In this system, good contact characteristics are hard to come. In the conventional staggered TFT, if the surface of the source/drain electrode is a metal film, as described above, the effect of PH3 plasma processing is small, and good contact characteristics are also rarely obtained. To the contrary, in the thin film transistor having the structure of the present invention, since polysilicon formed by laser irradiation is used for a contact layer between the source and drain electrodes, good contact characteristics can be easily obtained, and simultaneous processing of the pixel electrode and the signal line can be put into practical use.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.